`include "defines.v"
module mips(
	input wire clk,
	input wire rst,
	input wire[31:0] inst_i,
	input wire[31:0] ram_rdata_i, //从数据存储器读到的数据	
	input wire[5:0] int_i, //6个外部中断输入
	output wire rom_ce_o,
	output wire[31:0] rom_addr_o,
	
	output wire ram_ce_o, //数据存储器使能信号
	output wire ram_write_ce_o, //写使能信号
	output wire[31:0] ram_wdata_o, 
	output wire[31:0] ram_addr_o,
	output wire[3:0] ram_sel_o, //字节选择信号
	
	output wire timer_int_o //定时器中断信号
	//****************************
);
	//取指译码锁存器 译码模块连接线
	wire[31:0] if_id_lock_id_pc;
	wire[31:0] if_id_lock_id_inst;
	//******************************
	
	//译码寄存器堆模块连接线
	wire[31:0] id_regfile_reg1_data;
	wire[4:0] id_regfile_reg1_addr;
	wire id_regfile_reg1_read;
	
	wire[31:0] id_regfile_reg2_data;
	wire[4:0] id_regfile_reg2_addr;
	wire id_regfile_reg2_read;
	//******************************
	
	//译码 译码执行锁存器模块连接线
	wire[31:0] id_id_ex_lock_reg1;
	wire[31:0] id_id_ex_lock_reg2;
	wire[4:0] id_id_ex_lock_reg3_addr;
	wire id_id_ex_lock_reg3_write;
	wire[`AluOpWidth-1:0] id_id_ex_lock_alu_op;
	
	wire id_id_ex_lock_next_inst_is_in_delaySlot; //下一条进入译码阶段的指令是否是延迟槽指令
	wire[31:0] id_id_ex_lock_link_addr_o; //返回地址
	wire id_id_ex_lock_is_in_delaySlot; //当前译码阶段的指令是否是延迟槽指令
	wire id_ex_lock_id_is_in_delaySlot; //当前译码阶段的指令是否是延迟槽指令
	wire[31:0] id_id_ex_lock_inst;
		//异常相关
	wire[31:0] id_ie_ex_lock_exception_type;
	wire[31:0] id_ie_ex_lock_current_inst_addr;
	//******************************
	
	//译码执行锁存器 执行模块连接线
	wire[31:0] id_ex_lock_ex_reg1;
	wire[31:0] id_ex_lock_ex_reg2;
	wire[4:0] id_ex_lock_ex_reg3_addr;
	wire id_ex_lock_ex_reg3_write;
	wire[`AluOpWidth-1:0] id_ex_lock_ex_alu_op;
	wire id_ex_lock_ex_is_in_delaySlot; //当前执行阶段是否为延迟槽指令 
	wire[31:0] id_ex_lock_ex_link_addr_i; //返回地址
	wire[31:0] id_ex_lock_ex_inst;
	
		//异常相关
	wire[31:0] id_ex_lock_ex_exception_type;
	wire[31:0] id_ex_lock_ex_current_inst_addr;
	//***********************************
	
	//执行 执行访存锁存器模块连接线
	wire[31:0] ex_ex_mem_lock_write_data;
	wire[4:0] ex_ex_mem_lock_write_addr;
	wire ex_ex_mem_lock_write_ce;
		//与hilo寄存器相关信号	
	wire[31:0] ex_ex_mem_lock_hi;
	wire[31:0] ex_ex_mem_lock_lo;
	wire ex_ex_mem_lock_hilo_write_ce;
		//实现madd maddu msub msubu指令相关信号
	wire[63:0] ex_ex_mem_lock_hilo_temp; //ex送给锁存器的乘法结果
	wire[1:0] ex_ex_mem_lock_count; //ex送给锁存器的下个时钟周期处于第几个执行周期信号
	wire[63:0] ex_mem_lock_ex_hilo_temp; //锁存器送给ex的乘法结果
	wire[1:0] ex_mem_lock_ex_count; //锁存器送给ex的当前处于第几个执行周期信号
		//访存信号
	wire[31:0] ex_ex_mem_lock_addr;
	wire[31:0] ex_ex_mem_lock_wdata;
	wire[`AluOpWidth-1:0] ex_ex_mem_lock_alu_op;
		//CP0信号
	wire[31:0] ex_ex_mem_lock_cp0_wData;
	wire[4:0] ex_ex_mem_lock_cp0_wAddr;
	wire ex_ex_mem_lock_cp0_wCe;
		//异常信号
	wire[31:0] ex_ex_mem_lock_exception_type;
	wire[31:0] ex_ex_mem_lock_current_inst_addr;
	wire ex_ex_mem_lock_is_in_delaySlot;
	//***************************************
	
	
	//执行访存锁存器 访存模块连接线
	wire[31:0] ex_mem_lock_mem_write_data;
	wire[4:0] ex_mem_lock_mem_write_addr;
	wire ex_mem_lock_mem_write_ce;
	
		//与hilo寄存器相关信号	
	wire[31:0] ex_mem_lock_mem_hi;
	wire[31:0] ex_mem_lock_mem_lo;
	wire ex_mem_lock_mem_hilo_write_ce;
		//访存信号
	wire[31:0] ex_mem_lock_mem_addr;
	wire[31:0] ex_mem_lock_mem_wdata;
	wire[`AluOpWidth-1:0] ex_mem_lock_mem_alu_op;
		//CP0信号
	wire[31:0] ex_mem_lock_mem_cp0_wData;
	wire[4:0] ex_mem_lock_mem_cp0_wAddr;
	wire ex_mem_lock_mem_cp0_wCe;
	
		//异常信号
	wire[31:0] ex_mem_lock_mem_exception_type;
	wire[31:0] ex_mem_lock_mem_current_inst_addr;
	wire ex_mem_lock_mem_is_in_delaySlot;
	//***************************************
	
	//访存 访存回写锁存器模块连接线
	wire[31:0] mem_mem_wb_lock_write_data;
	wire[4:0] mem_mem_wb_lock_write_addr;
	wire mem_mem_wb_lock_write_ce;
	
	wire mem_mem_wb_lock_LLbit_wCe;
	wire mem_mem_wb_lock_LLbit_wData;
	//***********************************
	
	//访存回写锁存器 寄存器堆模块连接线
	wire[31:0] mem_wb_lock_regfile_write_data;
	wire[4:0] mem_wb_lock_regfile_write_addr;
	wire mem_wb_lock_regfile_write_ce;
	//************************************
	
	//译码 执行模块间 解决数据相关连接线
	wire[4:0] id_ex_write_addr;
	wire id_ex_write_ce;
	wire[31:0] id_ex_write_data;
	//***************************
	
	//译码 访存模块间 解决数据相关连接线
	wire[4:0] id_mem_write_addr;
	wire id_mem_write_ce;
	wire[31:0] id_mem_write_data;
	//***************************
	
	//hilo 执行模块间连接线
	wire[31:0] hilo_ex_hi;
	wire[31:0] hilo_ex_lo;
	//***************************
	
	//访存 访存回写锁存器间   访存 执行模块间连接线
		//hi lo
	wire[31:0] mem_mem_wb_lock_and_mem_ex_hi;
	wire[31:0] mem_mem_wb_lock_and_mem_ex_lo;
	wire mem_mem_wb_lock_and_mem_ex_hilo_write_ce;
		//cp0
	wire[31:0] mem_mem_wb_lock_and_ex_cp0_wData;
	wire[4:0] mem_mem_wb_lock_and_ex_cp0_wAddr;
	wire mem_mem_wb_lock_and_ex_cp0_wCe;
	//*******************************
	
	//访存回写锁存器 hilo间  访存回写锁存器 执行模块间连接线
	wire[31:0] mem_wb_lock_hilo_and_mem_wb_lock_ex_hi;
	wire[31:0] mem_wb_lock_hilo_and_mem_wb_lock_ex_lo;
	wire mem_wb_lock_hilo_and_mem_wb_lock_ex_hilo_write_ce;
	//**********************************
	
	//ctrl模块与其他模块连接线
	wire[5:0] ctrl_pause;
	wire pause_from_id;
	wire pause_from_ex;
	//*********************************
	//ex与div模块连接线
	wire div_ex_finish;
	wire[63:0] div_ex_result;
	wire[31:0] ex_div_data1;
	wire[31:0] ex_div_data2;
	wire ex_div_signed;
	wire ex_div_start;
	//***********************************
	//id与pc间连线
	wire[31:0] id_pc_jAddr; //跳转地址
	wire id_pc_jCe; //是否跳转
	//**************************
	//LLbit_reg与mem模块连接线
	wire LLbit_reg_mem_data;
	//***************************
	
	//ll,sc指令相关信号 访存回写锁存器向访存，LLbit寄存器发送的信号
	wire wb_mem_LLbit_wCe;
	wire wb_mem_LLbit_wData;
	//**************************************
	//访存写回锁存器向CP0，ex模块的信号
	wire[31:0] mem_wb_lock_cp0_and_ex_cp0_wData;
	wire[4:0] mem_wb_lock_cp0_and_ex_cp0_wAddr;
	wire mem_wb_lock_cp0_and_ex_cp0_wCe;
	//************************************
	//CP0与ex间连线
	wire[31:0] cp0_ex_data;
	wire[4:0] ex_cp0_addr;
	//*************************
	//CP0与mem间连线
	wire [31:0] cp0_mem_status;
	wire [31:0] cp0_mem_cause;
	wire [31:0] cp0_mem_epc;
	wire[31:0] mem_cp0_exception_type;
	wire[31:0] mem_cp0_current_inst_addr;
	wire mem_cp0_is_in_delaySlot;
	//**************************
	//mem与ctrl间连线
	wire[31:0] mem_ctrl_epc;
	//********************************
	//ctrl发出的异常相关信号
	wire ctrl_exception;
	wire[31:0] ctrl_exception_addr;
	//*******************************
	//取指模块实例化
	pc_reg pc_reg0(
		.clk(clk),
		.rst(rst),
		.pc(rom_addr_o),
		.ce(rom_ce_o),
		.pause(ctrl_pause), //流水线暂停信号
		.jAddr_i(id_pc_jAddr), //跳转到的地址
		.jCe_i(id_pc_jCe), //是否跳转
			//异常相关
		.exception(ctrl_exception), //异常发生信号
		.exception_addr(ctrl_exception_addr) //异常处理程序入口地址
	);

	
	//取指译码锁存器模块实例化
	if_id if_id0(
		.clk(clk),
		.rst(rst),
		.if_pc(rom_addr_o),
		.if_inst(inst_i),
		.id_pc(if_id_lock_id_pc),
		.id_inst(if_id_lock_id_inst),
		.pause(ctrl_pause), //流水线暂停信号
		.exception(ctrl_exception) //异常发生信号
	);
	
	
	//译码模块实例化
	id id0(
		.rst(rst),
		.pc_i(if_id_lock_id_pc),
		.inst_i(if_id_lock_id_inst),
		.reg1_data_i(id_regfile_reg1_data),
		.reg2_data_i(id_regfile_reg2_data),
		.reg1_addr_o(id_regfile_reg1_addr),
		.reg2_addr_o(id_regfile_reg2_addr),
		.reg1_read_o(id_regfile_reg1_read),
		.reg2_read_o(id_regfile_reg2_read),
		//传给id_ex模块的信号
		.reg1_o(id_id_ex_lock_reg1),
		.reg2_o(id_id_ex_lock_reg2),
		.reg3_addr_o(id_id_ex_lock_reg3_addr),
		.reg3_write_o(id_id_ex_lock_reg3_write),
		.alu_op_o(id_id_ex_lock_alu_op),
		// output reg[`AluSelWidth-1:0] alu_sel_o
		
		//执行模块传给译码模块的信号（解决数据相关）
		.ex_write_addr_i(id_ex_write_addr),
		.ex_write_ce_i(id_ex_write_ce),
		.ex_write_data_i(id_ex_write_data),
		//访存模块传给译码模块的信号（解决数据相关）
		.mem_write_addr_i(id_mem_write_addr),
		.mem_write_ce_i(id_mem_write_ce),
		.mem_write_data_i(id_mem_write_data),
		//控制流水线暂停信号
		.pause_o(pause_from_id),
		//转移分支指令相关信号
		.jAddr_o(id_pc_jAddr),
		.jCe_o(id_pc_jCe),
		.next_inst_is_in_delaySlot_o(id_id_ex_lock_next_inst_is_in_delaySlot), //下一条进入译码阶段的指令是否是延迟槽指令
		.link_addr_o(id_id_ex_lock_link_addr_o), //返回地址
		.is_in_delaySlot_o(id_id_ex_lock_is_in_delaySlot), //当前译码阶段的指令是否是延迟槽指令
		.is_in_delaySlot_i(id_ex_lock_id_is_in_delaySlot), //当前译码阶段的指令是否是延迟槽指令
		.inst_o (id_id_ex_lock_inst),
		.ex_alu_op_i(ex_ex_mem_lock_alu_op), //当前执行阶段的aluop
		//异常相关
		.exception_type_o(id_ie_ex_lock_exception_type), //异常类型
		.current_inst_addr_o(id_ie_ex_lock_current_inst_addr) //当前译码指令的地址
	);
	
	//译码执行锁存器模块实例化
	id_ex id_ex0(
		.clk(clk),
		.rst(rst),
		.id_reg1(id_id_ex_lock_reg1),
		.id_reg2(id_id_ex_lock_reg2),
		.id_reg3_addr(id_id_ex_lock_reg3_addr),
		.id_reg3_write(id_id_ex_lock_reg3_write),
		.id_alu_op(id_id_ex_lock_alu_op),
		// input wire[`AluSelWidth-1:0] id_alu_sel,
		.ex_reg1(id_ex_lock_ex_reg1),
		.ex_reg2(id_ex_lock_ex_reg2),
		.ex_reg3_addr(id_ex_lock_ex_reg3_addr),
		.ex_reg3_write(id_ex_lock_ex_reg3_write),
		.ex_alu_op(id_ex_lock_ex_alu_op),
		// output reg[`AluSelWidth-1:0] ex_alu_sel
		.pause(ctrl_pause), //流水线暂停信号
		//延迟槽相关信号
		.id_is_in_delaySlot_i(id_id_ex_lock_is_in_delaySlot), //当前译码阶段的指令是否是延迟槽指令
		.id_next_inst_is_in_delaySlot(id_id_ex_lock_next_inst_is_in_delaySlot), //下一条进入译码阶段的指令是否是延迟槽指令
		.id_link_addr(id_id_ex_lock_link_addr_o), //返回地址
		
		.ex_is_in_delaySlot(id_ex_lock_ex_is_in_delaySlot), //当前执行阶段的指令是否是延迟槽指令
		.id_is_in_delaySlot_o(id_ex_lock_id_is_in_delaySlot), //当前译码阶段的指令是否是延迟槽指令
		.ex_link_addr(id_ex_lock_ex_link_addr_i), //返回地址
		.id_inst(id_id_ex_lock_inst),
		.ex_inst(id_ex_lock_ex_inst),
		//异常相关
		.exception(ctrl_exception), //是否发生异常
		.id_exception_type_i(id_ie_ex_lock_exception_type), //异常类型
		.id_current_inst_addr_i(id_ie_ex_lock_current_inst_addr), //当前译码指令的地址
		.ex_exception_type_o(id_ex_lock_ex_exception_type), //异常类型
		.ex_current_inst_addr_o(id_ex_lock_ex_current_inst_addr) //当前执行指令的地址
	);
	
	//执行模块实例化
	ex ex0(
		.rst(rst),
		.reg1_i(id_ex_lock_ex_reg1),
		.reg2_i(id_ex_lock_ex_reg2),
		.reg3_addr_i(id_ex_lock_ex_reg3_addr),
		.reg3_write_i(id_ex_lock_ex_reg3_write),
		.alu_op_i(id_ex_lock_ex_alu_op),
		// input wire[`AluSelWidth-1:0] alu_sel_i,
		.write_data_o(ex_ex_mem_lock_write_data),
		.write_ce_o(ex_ex_mem_lock_write_ce),
		.write_addr_o(ex_ex_mem_lock_write_addr),
		
		//传给id模块的将要写的数据
		.ex_id_write_addr_o(id_ex_write_addr),
		.ex_id_write_ce_o(id_ex_write_ce),
		.ex_id_write_data_o(id_ex_write_data),
		
		//与hilo寄存器相关信号
		.hi_i(hilo_ex_hi),
		.lo_i(hilo_ex_lo),
		.mem_ex_hilo_write_ce_i(mem_mem_wb_lock_and_mem_ex_hilo_write_ce),
		.mem_ex_hi_i(mem_mem_wb_lock_and_mem_ex_hi),
		.mem_ex_lo_i(mem_mem_wb_lock_and_mem_ex_lo),
		.wb_ex_hilo_write_ce_i(mem_wb_lock_hilo_and_mem_wb_lock_ex_hilo_write_ce),
		.wb_ex_hi_i(mem_wb_lock_hilo_and_mem_wb_lock_ex_hi),
		.wb_ex_lo_i(mem_wb_lock_hilo_and_mem_wb_lock_ex_lo),
		.hi_o(ex_ex_mem_lock_hi),
		.lo_o(ex_ex_mem_lock_lo),
		.hilo_write_ce_o(ex_ex_mem_lock_hilo_write_ce),
		//控制流水线暂停信号
		.pause_o(pause_from_ex),
		.hilo_temp_i(ex_mem_lock_ex_hilo_temp), //第一个执行周期的乘法结果
		.count_i(ex_mem_lock_ex_count), //当前处于第几个执行周期
		.hilo_temp_o(ex_ex_mem_lock_hilo_temp), //第一个执行周期的乘法结果
		.count_o(ex_ex_mem_lock_count), //下一时钟周期处于执行阶段的第几个周期
		//除法相关信号
		.div_finish_i(div_ex_finish),
		.div_result_i(div_ex_result),
		.div_data1_o(ex_div_data1),
		.div_data2_o(ex_div_data2),
		.div_signed_o(ex_div_signed),
		.div_start_o(ex_div_start),
		//延迟槽信号
		.is_in_delaySlot_i(id_ex_lock_ex_is_in_delaySlot), //当前执行阶段是否为延迟槽指令 
		.link_addr_i(id_ex_lock_ex_link_addr_i), //返回地址
		//访存指令信号
		.inst_i(id_ex_lock_ex_inst),
		.alu_op_o(ex_ex_mem_lock_alu_op),
		.mem_addr_o(ex_ex_mem_lock_addr),
		.mem_wdata_o(ex_ex_mem_lock_wdata),
		//CP0相关信号
		.cp0_rData_i(cp0_ex_data),
		.mem_cp0_wData_i(mem_mem_wb_lock_and_ex_cp0_wData),
		.mem_cp0_wAddr_i(mem_mem_wb_lock_and_ex_cp0_wAddr),
		.mem_cp0_wCe_i(mem_mem_wb_lock_and_ex_cp0_wCe),
		.wb_cp0_wData_i(mem_wb_lock_cp0_and_ex_cp0_wData),
		.wb_cp0_wAddr_i(mem_wb_lock_cp0_and_ex_cp0_wAddr),
		.wb_cpo_wCe_i(mem_wb_lock_cp0_and_ex_cp0_wCe),
		.cp0_rAddr_o(ex_cp0_addr),
		.cp0_wData_o(ex_ex_mem_lock_cp0_wData),
		.cp0_wAddr_o(ex_ex_mem_lock_cp0_wAddr),
		.cp0_wCe_o(ex_ex_mem_lock_cp0_wCe),
		//异常相关
		.exception_type_i(id_ex_lock_ex_exception_type), //异常类型
		.current_inst_addr_i(id_ex_lock_ex_current_inst_addr), //当前执行指令的地址
		
		.exception_type_o(ex_ex_mem_lock_exception_type), //异常类型
		.current_inst_addr_o(ex_ex_mem_lock_current_inst_addr), //当前执行指令的地址
		.is_in_delaySlot_o(ex_ex_mem_lock_is_in_delaySlot) //执行阶段是否是延迟槽指令
	);
	
	
	//执行访存锁存器模块实例化
	ex_mem ex_mem0(
		.clk(clk),
		.rst(rst),
		.write_data_i(ex_ex_mem_lock_write_data),
		.write_ce_i(ex_ex_mem_lock_write_ce),
		.write_addr_i(ex_ex_mem_lock_write_addr),
		.write_data_o(ex_mem_lock_mem_write_data),
		.write_ce_o(ex_mem_lock_mem_write_ce),
		.write_addr_o(ex_mem_lock_mem_write_addr),
		//与hilo寄存器相关的数据
		.hi_i(ex_ex_mem_lock_hi),
		.lo_i(ex_ex_mem_lock_lo),
		.hilo_write_ce_i(ex_ex_mem_lock_hilo_write_ce),
		.hi_o(ex_mem_lock_mem_hi),
		.lo_o(ex_mem_lock_mem_lo),
		.hilo_write_ce_o(ex_mem_lock_mem_hilo_write_ce),
		.pause(ctrl_pause), //流水线暂停信号
		.hilo_temp_i(ex_ex_mem_lock_hilo_temp), //乘法结果
		.count_i(ex_ex_mem_lock_count), //下一个时钟周期是第几个执行周期
		.hilo_temp_o(ex_mem_lock_ex_hilo_temp), //乘法结果
		.count_o(ex_mem_lock_ex_count), //当前时钟周期处于执行阶段的第几个周期
		.mem_addr_i(ex_ex_mem_lock_addr),
		.mem_wdata_i(ex_ex_mem_lock_wdata),
		.alu_op_i(ex_ex_mem_lock_alu_op),
		.mem_addr_o(ex_mem_lock_mem_addr),
		.mem_wdata_o(ex_mem_lock_mem_wdata),
		.alu_op_o(ex_mem_lock_mem_alu_op),
		//CP0相关信号
		.ex_cp0_wData_i(ex_ex_mem_lock_cp0_wData),
		.ex_cp0_wAddr_i(ex_ex_mem_lock_cp0_wAddr),
		.ex_cp0_wCe_i(ex_ex_mem_lock_cp0_wCe),
		.mem_cp0_wData_o(ex_mem_lock_mem_cp0_wData),
		.mem_cp0_wAddr_o(ex_mem_lock_mem_cp0_wAddr),
		.mem_cp0_wCe_o(ex_mem_lock_mem_cp0_wCe),
		
		//异常相关
		.exception(ctrl_exception), //是否发生异常
		.ex_exception_type_i(ex_ex_mem_lock_exception_type), //异常类型
		.ex_current_inst_addr_i(ex_ex_mem_lock_current_inst_addr), //当前执行指令的地址
		.ex_is_in_delaySlot_i(ex_ex_mem_lock_is_in_delaySlot), //执行阶段是否是延迟槽指令
		
		.mem_exception_type_o(ex_mem_lock_mem_exception_type), //异常类型
		.mem_current_inst_addr_o(ex_mem_lock_mem_current_inst_addr), //当前访存阶段指令的地址
		.mem_is_in_delaySlot_o(ex_mem_lock_mem_is_in_delaySlot) //访存阶段是否是延迟槽指令
	);
		
	
	//访存模块实例化
	mem mem0(
		.rst(rst),
		.write_data_i(ex_mem_lock_mem_write_data),
		.write_ce_i(ex_mem_lock_mem_write_ce),
		.write_addr_i(ex_mem_lock_mem_write_addr),
		.write_data_o(mem_mem_wb_lock_write_data),
		.write_ce_o(mem_mem_wb_lock_write_ce),
		.write_addr_o(mem_mem_wb_lock_write_addr),
		
		//传给id模块的将要写的数据
		.mem_id_write_addr_o(id_mem_write_addr),
		.mem_id_write_ce_o(id_mem_write_ce),
		.mem_id_write_data_o(id_mem_write_data),
		
		//与hilo寄存器相关的数据
		.hi_i(ex_mem_lock_mem_hi),
		.lo_i(ex_mem_lock_mem_lo),
		.hilo_write_ce_i(ex_mem_lock_mem_hilo_write_ce),
		.hi_o(mem_mem_wb_lock_and_mem_ex_hi),
		.lo_o(mem_mem_wb_lock_and_mem_ex_lo),
		.hilo_write_ce_o(mem_mem_wb_lock_and_mem_ex_hilo_write_ce),
		//访存信号
		.alu_op_i(ex_mem_lock_mem_alu_op),
		.mem_addr_i(ex_mem_lock_mem_addr),
		.reg2_i(ex_mem_lock_mem_wdata),
		.mem_rdata_i(ram_rdata_i), //从数据存储器读到的数据
		.mem_ce_o(ram_ce_o), //数据存储器使能信号
		.mem_write_ce_o(ram_write_ce_o), //写使能信号
		.mem_wdata_o(ram_wdata_o), 
		.mem_addr_o(ram_addr_o),
		.byte_sel_o(ram_sel_o), //字节选择信号
		//ll,sc指令相关信号
		.LLbit_i(LLbit_reg_mem_data),
		.wb_LLbit_wCe_i(wb_mem_LLbit_wCe),
		.wb_LLbit_wData_i(wb_mem_LLbit_wData),
		.LLbit_wData_o(mem_mem_wb_lock_LLbit_wData),
		.LLbit_wCe_o(mem_mem_wb_lock_LLbit_wCe),
		//CP0相关信号
		.cp0_wData_i(ex_mem_lock_mem_cp0_wData),
		.cp0_wAddr_i(ex_mem_lock_mem_cp0_wAddr),
		.cp0_wCe_i(ex_mem_lock_mem_cp0_wCe),
		.cp0_wData_o(mem_mem_wb_lock_and_ex_cp0_wData),
		.cp0_wAddr_o(mem_mem_wb_lock_and_ex_cp0_wAddr),
		.cp0_wCe_o(mem_mem_wb_lock_and_ex_cp0_wCe),
		

		//异常相关
		.exception_type_i(ex_mem_lock_mem_exception_type), //异常类型
		.current_inst_addr_i(ex_mem_lock_mem_current_inst_addr), //当前访存阶段指令的地址
		.is_in_delaySlot_i(ex_mem_lock_mem_is_in_delaySlot), //访存阶段是否是延迟槽指令
			//CP0的输入
		.cp0_status_i(cp0_mem_status),
		.cp0_cause_i(cp0_mem_cause),
		.cp0_epc_i(cp0_mem_epc),
			//wb对CP0的信号
		.wb_cp0_wData_i(mem_wb_lock_cp0_and_ex_cp0_wData),
		.wb_cp0_wAddr_i(mem_wb_lock_cp0_and_ex_cp0_wAddr),
		.wb_cp0_wCe_i(mem_wb_lock_cp0_and_ex_cp0_wCe),

		
		.exception_type_o(mem_cp0_exception_type), //异常类型
		.current_inst_addr_o(mem_cp0_current_inst_addr), //当前访存阶段指令的地址
		.is_in_delaySlot_o(mem_cp0_is_in_delaySlot), //访存阶段是否是延迟槽指令
		.cp0_epc_o(mem_ctrl_epc) //CP0中EPC寄存器的最新值
	);
	
	
	mem_wb mem_wb0(
		.clk(clk),
		.rst(rst),
		.write_data_i(mem_mem_wb_lock_write_data),
		.write_ce_i(mem_mem_wb_lock_write_ce),
		.write_addr_i(mem_mem_wb_lock_write_addr),
		.write_data_o(mem_wb_lock_regfile_write_data),
		.write_ce_o(mem_wb_lock_regfile_write_ce),
		.write_addr_o(mem_wb_lock_regfile_write_addr),
		//与hilo寄存器相关的数据
		.hi_i(mem_mem_wb_lock_and_mem_ex_hi),
		.lo_i(mem_mem_wb_lock_and_mem_ex_lo),
		.hilo_write_ce_i(mem_mem_wb_lock_and_mem_ex_hilo_write_ce),
		.hi_o(mem_wb_lock_hilo_and_mem_wb_lock_ex_hi),
		.lo_o(mem_wb_lock_hilo_and_mem_wb_lock_ex_lo),
		.hilo_write_ce_o(mem_wb_lock_hilo_and_mem_wb_lock_ex_hilo_write_ce),
		.pause(ctrl_pause), //流水线暂停信号
		//ll,sc指令相关信号
		.LLbit_wCe_i(mem_mem_wb_lock_LLbit_wCe),
		.LLbit_wData_i(mem_mem_wb_lock_LLbit_wData),
		.LLbit_wCe_o(wb_mem_LLbit_wCe),
		.LLbit_wData_o(wb_mem_LLbit_wData),
		//异常相关
		.exception(ctrl_exception),		
		//CP0相关信号
		.cp0_wData_i(mem_mem_wb_lock_and_ex_cp0_wData),
		.cp0_wAddr_i(mem_mem_wb_lock_and_ex_cp0_wAddr),
		.cp0_wCe_i(mem_mem_wb_lock_and_ex_cp0_wCe),
		.cp0_wData_o(mem_wb_lock_cp0_and_ex_cp0_wData),
		.cp0_wAddr_o(mem_wb_lock_cp0_and_ex_cp0_wAddr),
		.cp0_wCe_o(mem_wb_lock_cp0_and_ex_cp0_wCe)
	);

	regfile regfile0(
		.clk(clk),
		.rst(rst),
		//写端口
		.waddr(mem_wb_lock_regfile_write_addr),
		.wdata(mem_wb_lock_regfile_write_data),
		.we(mem_wb_lock_regfile_write_ce),
		//读端口1
		.raddr1(id_regfile_reg1_addr),
		.re1(id_regfile_reg1_read),
		.rdata1(id_regfile_reg1_data),
		//读端口2
		.raddr2(id_regfile_reg2_addr),
		.re2(id_regfile_reg2_read),
		.rdata2(id_regfile_reg2_data)
	);

	hilo_reg hilo_reg0(
		.clk(clk),
		.rst(rst),
		.write_ce(mem_wb_lock_hilo_and_mem_wb_lock_ex_hilo_write_ce),
		.hi_i(mem_wb_lock_hilo_and_mem_wb_lock_ex_hi),
		.lo_i(mem_wb_lock_hilo_and_mem_wb_lock_ex_lo),
		.hi_o(hilo_ex_hi),
		.lo_o(hilo_ex_lo)
	);
	
	//流水线暂停控制模块实例化
	ctrl ctrl0(
		.rst(rst),
		.pause_from_id(pause_from_id),
		.pause_from_ex(pause_from_ex),
		.pause(ctrl_pause),
		//异常相关
		.cp0_epc_i(mem_ctrl_epc), //epc寄存器最新值
		.exception_type_i(mem_cp0_exception_type), //异常类型
		.exception_addr_o(ctrl_exception_addr), //异常处理程序入口地址
		.exception_o(ctrl_exception) //是否发生异常
	);
	
	//除法模块实例化
	div div0(
		.rst(rst),
		.clk(clk),
		.data1_i(ex_div_data1), //被除数
		.data2_i(ex_div_data2), //除数
		.signed_i(ex_div_signed), //是否为带符号除法(1:带符号)
		.start_i(ex_div_start), //开始信号
		.cancel_i(ctrl_exception), //取消信号
		.result_o(div_ex_result), //结果
		.finish_o(div_ex_finish) //是否运算完成
	);
	//LLbit_reg实例化
	LLbit_reg LLbit_reg0(
		.clk(clk),
		.rst(rst),
		.exception(ctrl_exception), //异常信号
		.wData_i(wb_mem_LLbit_wData),
		.wCe_i(wb_mem_LLbit_wCe),
		.data_o(LLbit_reg_mem_data)
	);
	//CP0寄存器实例化
	cp0_reg cp0_reg0(
		.clk(clk),
		.rst(rst),
		.writeCe_i(mem_wb_lock_cp0_and_ex_cp0_wCe), //是否写CP0中的寄存器
		.wAddr_i(mem_wb_lock_cp0_and_ex_cp0_wAddr), //要写的地址
		.wData_i(mem_wb_lock_cp0_and_ex_cp0_wData), //要写的数据
		
		.int_i(int_i), //6个外部中断输入
		//异常相关
		.exception_type_i(mem_cp0_exception_type), //发生异常的指令的异常类型
		.current_inst_addr_i(mem_cp0_current_inst_addr), //发生异常的指令的地址
		.is_in_delaySlot_i(mem_cp0_is_in_delaySlot), //发生异常的指令是否是延迟槽指令
		.rAddr_i(ex_cp0_addr), //要读寄存器的地址
		.data_o(cp0_ex_data), //读出的数据
		// output reg[31:0] count_o(), //Count寄存器的值
		// output reg[31:0] compare_o(), //Compare寄存器的值
		.status_o(cp0_mem_status), //Status寄存器的值
		.cause_o(cp0_mem_cause), //Cause寄存器的值
		.epc_o(cp0_mem_epc), //EPC寄存器的值
		

		// output reg[31:0] prid_o(), //PRId寄存器的值
		// output reg[31:0] config_o(), //Config寄存器的值
		.timer_int_o(timer_int_o) //定时中断发生
	);
	
endmodule